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? semiconductor components industries, llc, 2011 june, 2011 ? rev. 1 1 publication order number: NCV8769/d NCV8769 ultra low iq 150 ma ldo regulator with reset and early warning the NCV8769 is 150 ma ldo regulator with integrated reset and early warning functions dedicated for microprocessor applications. its robustness allows NCV8769 to be used in severe automotive environments. ultra low quiescent current as low as 25 a typical for NCV8769 makes it suitable for applications permanently connected to battery requiring ultra low quiescent current with or without load. the NCV8769 contains protection functions as current limit, thermal shutdown and reverse output current protection. features ? output voltage options: 5 v ? output voltage accuracy: 2% ? output current up to 150 ma ? ultra low quiescent current: ? typ 25 a for adjustable early warning threshold option ? very low dropout voltage ? microprocessor compatible control functions: ? reset with adjustable power ? on delay ? early warning ? wide input voltage operation range: up to 40 v ? protection features: ? current limitation ? thermal shutdown ? these are pb ? free devices typical applications ? body control module ? instruments and clusters ? occupant protection and comfort ? powertrain figure 1. application circuit si so dt ro gnd NCV8769y0 microprocessor v bat 0.1 f c in reset i/o 1 f c out v out v in r si1 v dd r si2 http://onsemi.com http://onsemi.com ordering information marking diagrams see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. so ? 14 d suffix case 751a 1 14 v8769yzxxg awlywwg 1 14 y = timing and reset threshold option* z = early warning option* xx = voltage option 5.0 v (xx = 50) a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package *see application information section.
NCV8769 http://onsemi.com 2 driver with current limit thermal shutdown vout gnd timing circuit and reset output driver and sense output driver vin ro si so dt v ref * figure 2. simplified block diagram *pull ? down resistor (~150 k ) active only in reset state. ** 5 v option only. v ref ** **
NCV8769 http://onsemi.com 3 gnd gnd ro gnd gnd gnd gnd 114 gnd so ? 14 dt nc so si vout vin figure 3. pin connections (top view) pin function description pin no. pin name description 1 nc not connected 2 dt reset delay time select. short to gnd or connect to v out to select time. 3, 4, 5, 6, 10, 11, 12 gnd power supply ground. 7 ro reset output. 30 k internal pull ? up resistor connected to v out . ro goes low when v out drops by more than 7% (typ.) from its nominal value. 8 so early warning output. 30 k internal pull ? up resistor connected to v out . it can be used to provide early warning of an impending reset condition. leave open if not used. 9 v out regulated output voltage. connect 1 f capacitor with esr < 100 to ground. 13 v in positive power supply input. connect 0.1 f capacitor to ground. 14 si sense input; if not used, connect to v out . see electrical characteristics table and application information sections for more information.
NCV8769 http://onsemi.com 4 absolute maximum ratings rating symbol min max unit input voltage dc (note 1) v in ? 0.3 40 v input voltage transient (note 1) v in ? 45 v input current i in ? 5 ? ma output voltage (note 2) v out ? 0.3 5.5 v output current i out ? 3 current limited ma dt (reset delay time select) voltage v dt ? 0.3 5.5 v dt (reset delay time select) current i dt ? 1 1 ma reset output voltage v ro ? 0.3 5.5 v reset output current i ro ? 3 3 ma sense input voltage dc v si ? 0.3 40 v sense input voltage transient v si ? 45 v sense input current i si ? 1 1 ma sense output voltage v so ? 0.3 5.5 v sense output current i so ? 3 3 ma maximum junction temperature t j(max) ? 40 150 c storage temperature t stg ? 55 150 c esd capability, human body model (note 3) esd hbm ? 2 2 kv esd capability, machine model (note 3) esd mm ? 200 200 v lead temperature soldering reflow (smd styles only) (note 4) t sld ? 265 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristis and application information for safe operating area. 2. 5.5 or (v in + 0.3 v), whichever is lower 3. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) 4. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d
NCV8769 http://onsemi.com 5 thermal characteristics rating symbol value unit thermal characteristics, so ? 14 (note 5) thermal resistance, junction ? to ? air (note 6) thermal reference, junction ? to ? pin4 (note 6) r ja jp4 94 18 c/w 5. refer to electrical characteristis and application information for safe operating area. 6. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. operating ranges (note 7) rating symbol min max unit input voltage (note 8) v in 5.5 40 v junction temperature t j ? 40 150 c 7. refer to electrical characteristis and application information for safe operating area. 8. minimum v in = 5.5 v or (v out + v do ), whichever is higher. electrical characteristics v in = 13.2 v, v dt = gnd, v si = v out , r si1 & r si2 not used, c in = 0.1 f, c out = 1 f, for typical values t j = 25 c, for min/max values t j = ? 40 c to 150 c; unless otherwise noted. (notes 9 and 10) parameter test conditions symbol min typ max unit regulator output output voltage (accuracy %) v in = 5.6 v to 40 v, i out = 0.1 ma to 100 ma v in = 5.8 v to 16 v, i out = 0.1 ma to 150 ma v out 4.9 4.9 ( ? 2 %) 5.0 5.0 5.1 5.1 (+2%) v output voltage (accuracy %) t j = ? 40 c to 125 c v in = 5.8 v to 28 v, i out = 0 ma to 150 ma v out 4.9 ( ? 2 %) 5.0 5.1 (+2%) v line regulation v in = 6 v to 28 v, i out = 5 ma reg line ? 20 0 20 mv load regulation i out = 0.1 ma to 150 ma reg load ? 40 10 40 mv dropout voltage (note 11) i out = 100 ma i out = 150 ma v do ? ? 225 300 450 600 mv output capacitor for stability (note 12) i out = 0 ma to 150 ma c out esr 1.0 0.01 ? ? 100 100 f quiescent currents quiescent current, i q = i in ? i out i out = 0.1 ma, t j = 25 c i out = 0.1 ma to 150 ma, t j 125 c i q ? ? 25 ? 31 33 a current limit protection current limit v out = 0.96 x v out_nom i lim 205 ? 525 ma short circuit current limit v out = 0 v i sc 205 ? 525 ma psrr power supply ripple rejection (note 12) f = 100 hz, 0.5 v pp psrr ? 60 ? db dt (reset delay time select) dt threshold voltage logic low logic high v th(dt) ? 2 ? ? 0.8 ? v dt input current v dt = 5 v i dt ? ? 1 a 9. refer to absolute maximum ratings and application information for safe operating area. 10. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t a t j . low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 11. measured when output voltage falls 100 mv below the regulated voltage at v in = 13.2 v. 12. values based on design and/or characterization. 13. see application information section for reset thresholds and reset delay time options.
NCV8769 http://onsemi.com 6 electrical characteristics v in = 13.2 v, v dt = gnd, v si = v out , r si1 & r si2 not used, c in = 0.1 f, c out = 1 f, for typical values t j = 25 c, for min/max values t j = ? 40 c to 150 c; unless otherwise noted. (notes 9 and 10) parameter unit max typ min symbol test conditions reset output ro output voltage reset threshold (note 13) v out decreasing v in > 5.5 v v rt 90 93 96 %v out reset hysteresis v rh ? 2.0 ? %v out maximum reset sink current v out = 4.5 v, v ro = 0.25 v i romax 1.75 ? ? ma reset output low voltage v out > 1 v, i ro < 200 a v rol ? 0.15 0.25 v reset output high voltage v roh 4.5 ? ? v integrated reset pull up resistor r ro 15 30 50 k reset delay time (note 13) dt connected to gnd dt connected to v out t rd 12.8 25.6 16 32 19.2 38.4 ms reset reaction time (see figure 29) t rr 16 25 38 s early warning (si and so) sense input threshold (NCV8769y0) high low v si(th) 1.25 1.20 1.33 1.25 1.40 1.33 v sense input current (NCV8769y0) v si = 5 v i si ? 1 0.1 1 a integrated sense output pull up resistor r so 15 30 50 k sense output low voltage v si < 1.2 v, i so < 200 a, v out > 1 v v sol ? 0.15 0.25 v sense output high voltage v soh 4.5 ? ? v maximum sense output sink current v out = 4.5 v, v si < 1.2 v, v so = 0.25 v i somax 1.75 ? ? ma si high to so high reaction time v si increasing t psolh ? 7 12 s si low to so low reaction time v si decreasing t psohl ? 3.8 5.0 s thermal shutdown thermal shutdown temperature (note 12) t sd 150 175 195 c thermal shutdown hysteresis (note 12) t sh ? 25 ? c 9. refer to absolute maximum ratings and application information for safe operating area. 10. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t a t j . low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 11. measured when output voltage falls 100 mv below the regulated voltage at v in = 13.2 v. 12. values based on design and/or characterization. 13. see application information section for reset thresholds and reset delay time options.
NCV8769 http://onsemi.com 7 typical characteristics 20 21 22 23 24 25 26 27 28 29 30 ? 40 ? 20 0 20 40 60 80 100 120 140 160 figure 4. quiescent current vs. temperature t j , junction temperature ( c) i q , quiescent current ( a) v in = 13.2 v i out = 100 a figure 5. quiescent current vs. input voltage v in , input voltage (v) i q , quiescent current ( a) i out = 0 ma t j = 25 c figure 6. quiescent current vs. output current i q , quiescent current ( a) i out , output current (ma) t j = 25 c t j = ? 40 c t j = 150 c figure 7. output voltage vs. temperature 4.90 4.95 5.00 5.05 5.10 ? 40 ? 20 0 20 40 60 80 100 120 140 160 v in = 13.2 v i out = 100 a t j , junction temperature ( c) v out , output voltage (v) figure 8. output voltage vs. input voltage 0 1 2 3 4 5 6 012345678 v out , output voltage (v) v in , input voltage (v) i out = 1.0 ma t j = 25 c t j = ? 40 c t j = 150 c figure 9. dropout vs. output current 0 100 200 300 400 500 0 25 50 75 100 125 150 v do , dropout voltage (mv) i out , output current (ma) t j = 150 c t j = 25 c t j = ? 40 c 22 23 24 25 26 27 28 29 30 20 21 0 25 50 75 100 125 150 0 50 100 150 200 0 5 10 15 20 25 30 35 40 250 300 v in = 13.2 v
NCV8769 http://onsemi.com 8 typical characteristics figure 10. dropout vs. temperature 0 100 200 300 400 500 ? 40 ? 20 0 20 40 60 80 100 120 140 160 v do , dropout voltage (mv) t j , junction temperature ( c) i out = 150 ma i out = 100 ma figure 11. output current limit vs. input voltage 0 100 200 300 400 0 5 10 15 20 25 30 35 40 v in , input voltage (v) i lim , i sc , current limit (ma) t j = 25 c i sc @ v out = 0 v i lim @ v out = 4.8 v figure 12. output current limit vs. temperature 200 250 300 350 400 ? 40 ? 20 0 20 40 60 80 100 120 140 160 i lim , i sc , current limit (ma) t j , junction temperature ( c) i sc @ v out = 0 v i lim @ v out = 4.8 v v in = 13.2 v figure 13. c out esr stability vs. output current 0.01 0.1 1 10 100 0 50 100 150 200 250 300 350 i out , output current (ma) esr, stability region ( ) stable region v in = 13.2 v t j = ? 40 c to 150 c c out = 1 f ? 100 f time (500 s/div) 12.2 v 14.2 v 4.97 v 5.08 v 5 v 13 v figure 14. line transients v in (1 v/div) v out (50 mv/div) t j = 25 c i out = 1 ma c out = 10 f t rise/fall = 1 s (v in ) figure 15. load transients t j = 25 c v in = 13.2 v c out = 10 f t rise/fall = 1 s (i out ) i out (100 ma/div) v out (200 mv/div) 150 ma 4.79 v 5.15 v 5 v 0.1 ma time (20 s/div)
NCV8769 http://onsemi.com 9 typical characteristics time (100 ms/div) figure 16. power up and down transient v in (5 v/div) v out (5 v/div) v ro (5 v/div) v so (5 v/div) t j = 25 c r out = 5 k figure 17. psrr vs. frequency 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 10000 0 f, frequency (hz) psrr (db) t j = 25 c v in = 13.2 v 0.5 v pp c out = 1 f i out = 1 ma figure 18. reset threshold vs. temperature 4.60 4.65 4.70 4.75 4.80 ? 40 ? 20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c) v rt , reset threshold (v) v in = 13.2 v 10 ? 40 ? 20 0 20 40 60 80 100 120 140 16 0 figure 19. reset time vs. temperature t j , junction temperature ( c) t rd , reset delay time (ms) v in = 13.2 v v dt = v out v dt = gnd 1.36 ? 40 ? 20 0 20 40 60 80 100 120 140 160 sense input voltage (v) figure 20. si threshold vs. temperature t j , junction temperature ( c) v si_(th),h (v si increasing) v si_(th),l (v si decreasing) 1.34 1.32 1.3 1.28 1.26 1.24 1.22 40 35 30 25 20 15
NCV8769 http://onsemi.com 10 v in t v out t v ro t v rt +v rh NCV8769 http://onsemi.com 11 definitions general all measurements are performed using short pulse low duty cycle techniques to maintain junction temperature as close as possible to ambient temperature. output voltage the output voltage parameter is defined for specific temperature, input voltage and output current values or specified over line, load and temperature ranges. line regulation the change in output voltage for a change in input voltage measured for specific output current over operating ambient temperature range. load regulation the change in output voltage for a change in output current measured for specific input voltage over operating ambient temperature range. dropout voltage the input to output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. it is measured when the output drops 100 mv below its nominal value. the junction temperature, load current, and minimum input supply requirements affect the dropout level. quiescent current quiescent current (i q ) is the difference between the input current (measured through the ldo input pin) and the output load current. current limit and short circuit current limit current limit is value of output current by which output voltage drops below 96% of its nominal value. it means that the device is capable to supply minimum 200 ma without sending reset signal to microprocessor. short circuit current limit is output current value measured with output of the regulator shorted to ground. psrr power supply rejection ratio is defined as ratio of output voltage and input voltage ripple. it is measured in decibels (db). line transient response typical output voltage overshoot and undershoot response when the input voltage is excited with a given slope. load transient response typical output voltage overshoot and undershoot response when the output current is excited with a given slope between low ? load and high ? load conditions. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. when activated at typically 175 c, the regulator turns off. this feature is provided to prevent failures from accidental overheating. maximum package power dissipation the power dissipation level is maximum allowed power dissipation for particular package or power dissipation at which the junction temperature reaches its maximum operating value, whichever is lower.
NCV8769 http://onsemi.com 12 applications information the NCV8769 regulator is self ? protected with internal thermal shutdown and internal current limit. typical characteristics are shown in figures 4 to 22. input decoupling (c in ) a ceramic or tantalum 0.1 f capacitor is recommended and should be connected close to the NCV8769 package. higher capacitance and lower esr will improve the overall line and load transient response. if extremely fast input voltage transients are expected then appropriate input filter must be used in order to decrease rising and/or falling edges below 50 v/ s for proper operation. the filter can be composed of several capacitors in parallel. output decoupling (c out ) the NCV8769 is a stable component and does not require a minimum equivalent series resistance (esr) for the output capacitor. stability region of esr vs. output current is shown in figure 13. the minimum output decoupling value is 1 f and can be augmented to fulfill stringent load transient requirements. the regulator works with ceramic chip capacitors as well as tantalum devices. larger values improve noise rejection and load transient response. reset delay time select selection of the NCV8769yz devices and the state of the dt pin determines the available reset delay times. the part is designed for use with dt tied to ground or out, but may be controlled by any logic signal which provides a threshold between 0.8 v and 2 v. the default condition for an open dt pin is the slower reset time (dt = gnd condition). times are in pairs and are highlighted in the chart below. consult factory for availability. the delay time select (dt) pin is logic level controlled and provides reset delay time per the chart. note the dt pin is sampled only when ro is low, and changes to the dt pin when ro is high will not effect the reset delay time. reset operation a reset signal is provided on the reset output (ro) pin to provide feedback to the microprocessor of an out of regulation condition. the timing diagram of reset function is shown in figure 21. this is in the form of a logic signal on ro. output voltage conditions below the reset threshold cause ro to go low. the ro integrity is maintained down to v out = 1.0 v. the reset output (ro) circuitry includes internal pull ? up connected to the output (v out ) no external pull ? up is necessary. reset signal is also generated in case when input voltage decreases below its minimum operating limit. reset delay and reset threshold options part number dt = gnd reset time dt = v out reset time reset threshold NCV87695z 16 ms 32 ms 93% note: the timing values can be selected from following list: 8, 16, 32, 64, 128 ms. the reset threshold values can be selected from the following list: 90% and 93%. contact factory for other timing combinations not included in the table. sense input (si)/sense output (so) voltage monitor an on-chip comparator is available to provide early warning to the microprocessor of a possible reset signal. the reset signal typically turns the microprocessor off instantaneously. this can cause unpredictable results with the microprocessor. the signal received from the so pin will allow the microprocessor time (t warning ) to complete its present task before shutting down. this function is performed by a comparator referenced to the band gap voltage. the actual trip point can be programmed externally using a resistor divider to the input monitor (si). (see figure 1) the values for r si1 and r si2 are selected for a typical threshold of 1.2 v on the si pin according to equations 1 and 2, where v in_ew(th) is demanded value of input voltage at which early warning signal has to be generated. r si2 is recommended to be selected in range of 100 k to 1 m . the higher are values of resistors r si1 and r si2 the lower is current flowing through the resistor divider, however this also increases a delay between input voltage and si input voltage caused by charging si input capacitance with higher rc constant. the delay can be lowered by decreasing the resistors values with consequence of resistor divider current is increased. v in_ew(th) 1.25 1 r si1 r si2 (eq. 1) r si1 r si2 v in_ew(th) 1.2 1 (eq. 2) sense output the sense output is from an open drain driver with an internal 30 k pull up resistor to v out . figure 23 shows the so monitor timing waveforms as a result of the circuit depicted in figure 1. if the input voltage decreases the output voltage decreases as well. if the si input low threshold voltage is crossed it causes the voltage on the so output goes low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. t wa r n i n g is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal.
NCV8769 http://onsemi.com 13 v out v si v si,low v ro v so t warning figure 23. so warning timing diagram t psolh t psohl t t sense input v si,high v si,low sense output high low figure 24. sense input to sense output timing diagram thermal considerations as power in the NCV8769 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the NCV8769 has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power applications. the maximum dissipation the NCV8769 can handle is given by: p d(max) t j(max) t a
r ja (eq. 3) since t j is not recommended to exceed 150 c, then the NCV8769 soldered on 645 mm 2 , 1 oz copper area, fr4 can dissipate up to 1.33 w when the ambient temperature (t a ) is 25 c. see figure 25 for r thja versus pcb area. the power dissipated by the NCV8769 can be calculated from the following equations: p d v in i q @i out i out v in v out (eq. 4) or v in(max) p d(max) v out i out i out i q (eq. 5) figure 25. thermal resistance vs. pcb copper area 60 70 80 90 100 110 120 0 100 200 300 400 500 600 700 r ja , thermal resistance ( c/w) copper heat spreader area (mm 2 ) pcb 2 oz cu pcb 1 oz cu hints v in and gnd printed circuit board traces should be as wide as possible. when the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. place external components, especially the output capacitor, as close as possible to the NCV8769 and make traces as short as possible. ordering information device output voltage reset delay time dt = gnd/v out reset threshold (typ) marking package shipping ? NCV876950d250r2g 5.0 v 16/32 ms 93 % v87695050g so ? 14 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d
NCV8769 http://onsemi.com 14 package dimensions soic ? 14 case 751a ? 03 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint 7x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCV8769/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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